Figure 1 (a) Charge state relaxation times for a 2-P-atom device with a spacing of 50nm, deduced from pulsed gate measurements, together with theoretical prediction for 50 nm donor separation. (b) Fourier transforms of bias dependence reveal peaks due to phonon interference on a length scale of ~ 50 nm.	Figure 2 Highly conducting, planar nanowires in silicon. (a) I-V characteristics of P nanowires down to 27nm in width giving resistances as low as 50k and ohmic behaviour at 4K. (b) A table comparing wire resistances with other silicon nanowires in the literature showing how the resistances of our wires are nearly an order of magnitude lower.

The past year saw important progress across all of the Centre’s eleven experimental and seven theoretical research programs, with 100 papers published in, or accepted for, peer-reviewed journals in 2005, and a further 13 submitted. The development of spin-based qubits in the Si:P materials system is the key focus of the Centre’s solid-state programs.

Silicon-based Si:P Qubits via Ion Implantation
As a stepping stone to spin-based qubits, a charge-based Si:P architecture has been proposed by Centre researchers for which fast single charge readout is accessible now, using rf-SET technology established within the Centre. Although a charge-based qubit will decohere faster that its spin-based counterparts, the readout signal generated during electron transfer is similar to that used for spin readout schemes and as such provides a critical test bed for the development of spin qubits.

During 2005 the first experiments that address the relevant energy and time scales for Si:P charge qubits were performed. In particular we performed microwave spectroscopy on few-atom devices and measured inelastic tunnelling rates between two phosphorus atoms. By studying the dynamical response between individual phosphorus donors or P-clusters using gate voltage pulses or imposing a GHz microwave field, we are able to gain information about the charge state relaxation time, and energy level spectrum, respectively.

A key result comes from a device implanted with exactly two atoms, which showed an extremely stable charge transfer event. Dynamic measurements were performed by pulsing the gate voltage, yielding remarkably long charge state relaxation times of order 10 ms. A remarkable match to theoretical predictions for combined resonant and phonon assisted tunnelling was found – see Figure 1a. Evidence of oscillatory behaviour due to interference with acoustic phonons is confirmed by Fourier transformation (Figure 1b), which is consistent with the expected donor spacing of 50 nm. These results represent the first conclusive measurement of single electron transfer in an atomically-engineered Si:P device.

Figure 3 Electrical characterisation of 80nm dot device. (a) Cross section schematic. (b) STM image of 80nm dot defined between source and drain leads on one atomic terrace of the Si(100) surface. (c) I-V characteristics through the dot for four different contact configurations at 4K. (d) Differential conductance across the device, showing large blockade region and resonant tunnelling on and off the island.

Silicon-based Si:P Qubits via Scanning Probe Microscopy
Following our success in developing a complete fabrication strategy to pattern dopants in silicon with atomic precision using scanning probe microscopy, the group has recently succeeded in fabricating two key components of the qubit architecture. First we demonstrate that we can form the narrowest wires in silicon that still conduct and exhibit ohmic behaviour. These wires will act as the source-drain leads for electrical transport measurements through quantum dot systems leading to both spin and charge detection. Four-terminal electrical measurements of these wires measured at 4K (in Figure 2a), reveal ohmic behaviour with resistances ~ 50 k? for wire widths down to 27 nm. The resistance of these wires is nearly an order of magnitude lower than wires of similar dimensions produced by other technologies (see Figure 2b).

Secondly we have developed a fabrication strategy to realize few atom dot devices, with the ultimate goal of fabricating few and single P atoms between source-drain leads to investigate the control of individual quantum mechanical charge and spin states.

Figure 3 shows electrical results from a device consisting of an 80 nm diameter dot with source-drain leads separated by a gap of ~20nm. By substrate patterning we have demonstrated that we can fabricate the active component of the device on one atomic plane of the silicon substrate STM (see Figure 3b). Electrical transport measurements at 4K through the device in Figure 3(c) show a highly reproducible blockade region between source-drain voltages of ±700 mV. In addition there is a clear peak in the differential conductance, shown in Figure 3(d) corresponding to charge transfer across the island. These results are extremely promising with work underway to reduce the size of the island towards the few electron level, where it is anticipated that discrete quantum levels will be observed.