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| Figure 1. STM fabricated
quantum wire. (A) Optical microscope image of the completed
device. (B) and (C) SEM images of the STM tip aligned to registration
markers. (D) STM image of a nano-wire created by STM. |
In 2004 the Centre for Quantum Computer Technology was expanded
to become an ARC Centre of Excellence (COE). The COE involves 18
research programs across 6 Australian Universities, (Universities
of NSW, Melbourne, Queensland, Sydney, Griffith, Macquarie), the
Australian Defence Force Academy and the Department of Defence.
Research at UNSW is focussed on electronic silicon-based solid
state quantum computing in which the quantum bits (qubits) are comprised
of single phosphorus atoms embedded in silicon, with quantum information
encoded onto the spin or charge state of the atoms.
Constructing these atomic-scale devices is a major challenge, and
UNSW houses some of Australia’s most advanced capabilities
in nanotechnology. Device fabrication is being pursued using two
parallel strategies: a “top-down” approach using single
ion implantation, and a “bottom-up” approach which uses
scanned probe lithography and epitaxial semiconductor growth to
achieve atomically precise construction.
During 2003 a number of key milestones were achieved:
• We showed that it is possible to incorporate individual
phosphorus dopants into a silicon surface with atomic precision
with an STM (scanning tunnelling microscope), a key requirement
for making qubit arrays.
• We demonstrated a new technique to construct silicon devices
with atomic precision using UNSW’s new STM/ MBE system, and
used to construct a fully functional quantum wire in silicon.
• We constructed ion-implanted Si:P double quantum dot devices
to demonstrate gate-controlled single electron transfer, a key requirement
for all Si-based qubits.
• We demonstrated coincident detection of single electron
transfer between buried Si:P quantum dots using two single electron
transistors, and used radio-frequency electronics to allow detection
on ms timescales.
• We developed high-level logic design for high speed circuitry
required to control a quantum processor, facilitating operation
of general quantum algorithms.
“Bottom-up” STM fabricated devices
This approach involves using an STM tip to position single P dopant
atoms in silicon in an ordered atomic array before they are encapsulated
in high quality crystalline silicon grown by MBE. In 2003 we published
our work demonstrating the incorporation of single P atoms in silicon
with atomic precision.
A second highlight was the construction of a fully functional nanoscale
device using the custom-built STM-SEM-MBE system that was installed
at UNSW in late 2002. This enabled the development of the first
registration process that allows us to locate and make electrical
contact to an STM-patterned device once it is outside the vacuum
environment. Figure 1 shows a schematic of a quantum wire constructed
with this process. Low temperature magnetoresistance studies of
a 4 × 4 µm square and a 90 nm-wide quantum wire showed
clear differences between the electrical properties of these two
devices, revealing a beautiful demonstration of the cross-over from
two-dimensional to one-dimensional electron transport in a quantum
wire as the temperature is reduced. These results open the way to
creating single atom electronic devices with the STM.
Single electron motion in “Top-Down” Si:P test devices
In 2003 we constructed and demonstrated a novel double quantum
dot structure in silicon using phosphorus ion implantation, a critical
test device to assess the potential of Si:P qubits (Figure 2a).
Application of a differential bias to the surface gates causes periodic
single electron tunneling between the two dots, which is detected
with two nearby single electron transistors (SETs) as a discontinuous
step in the SET current (Figure 2b). This signal repeats periodically,
and using two SETs makes it is possible to detect the charge transfer
in coincidence, ensuring that the signal is coming from the vicinity
of the double dot system.
Single atom devices were fabricated using the Centre’s single-ion
implantation technology, which uses in-situ ion detector electrodes
to produce a signal each time a P+ ion enters the device.
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| Figure 2. a) Micrograph of ion-implanted
twin-SET double quantum dot device with an adjacent AFM image
of the central gate area. b) Measurements with an rf-SET of
quasi-periodic electron transfer in this device, obtained as
a function of time while a differential bias is applied to gates
B and SR. |
Figure 3. Characterisation of rf-SETs. a)
Bias spectroscopy of a rf-SET in the superconducting state (B = 0)
where ? is the superconducting gap for Al. b) Single-shot response
of the rf-SET to a small step in gate voltage creating an induced
charge 0.1e at the SET island. |
Quantum Measurement: High speed single electron transistors
Measurement of quantum bits will require extremely sensitive electrometers
able to detect a fraction of an electron charge on sub-microsecond
timescales. We have developed twin radio-frequency single electron
transistors and were able to detect single electrons moving between
two buried Si:P dots on microsecond timescales (Figure 3). These
results show that it is possible to read-out the state of silicon
based qubits, and augur well for the future.
Alex Hamilton, Michelle Simmons
and Robert Clark
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