The goal of constructing a prototype QC device has been approached using two parallel strategies. The first is by the ‘bottom up’ program in which the devices are built atomic layer by atomic layer, using scanned probe lithography and epitaxial semiconductor growth. The second is the ‘top down’ program in which single qubits are implanted into the device through electron beam lithography defined masks, with integrated detectors used to register single ion implantation events. Both approaches require nanometer-scale control gates on the surface of the device to manipulate the qubits (nuclear or electron spin) and fast single electron transistors (SET) for read-out.

Atomic Fabrication and Crystal Growth
Following our success last year in the creation of an atomically ordered array of phosphorus atoms on the surface of silicon the next major hurdle in the Atomic Fabrication Program has been to encapsulate this array in high quality silicon crystal without them diffusing out of the carefully created array. This has been approached using a combination of STM imaging and cryogenic electrical measurement. Our program reports three highlights this year.

Firstly, using dual bias STM (Scanning Tunnelling Microscope) imaging it has been possible to identify the phosphorus incorporation mechanism into a clean silicon surface. These images show that when a PH3 dosed silicon surface is heated, the phosphorus atoms substitute for a surface silicon atom - a critical anneal step that incorporates the phosphorus atoms into the surface with three covalent bonds rather than just one. As a result the phosphorus atoms are directionally incorporated into the surface whilst the carefully patterned atomic arrays are maintained.

Figure1 Left: Two phosphine molecules adsorbed to a clean silicon surface Right: P incorporation into the top layer of silicon after heating

Secondly, the first 2D electron samples were grown in the MBE system by the use of a delta doped phosphorus layer in silicon. Within experimental error we were able to show that the 2D carrier density determined from Hall effect measurements was identical to the total number of deposited atoms, demonstrating that the majority of the phosphorus dopants are sitting in substitutional sites.

Figure 2: STM images of the various stages in preparation of a 2D delta doped phosphorus in silicon sample showing (a) a clean surface (b) after phosphine dosing and annealing (c) silicon encapsulation at room temperature and (d) annealing the surface at ~300oC. (e, f) show the electrical characterisation of the 2D layer.

Thirdly, the focus of the experimental program has now turned to the fabrication of atomically patterned phosphorus arrays in silicon. It is difficult to find atomic size patches on the surface of the wafer using the STM. Creating registration marks in hydrogen we have demonstrated that it is possible to consistently locate the same part of the surface. The final encapsulation of the STM-patterned atomic array is now within our sights.

Figure 3: Controlled registration markers fabricated by STM lithography allow us to find the atomically patterned array after dosing and annealing. The hydrogen resist acts as a perfect barrier to phosphorus diffusion during heating.

Top Down Ion Implantation
An important breakthrough occurred this year with the ability to electrically detect single ion impacts during the implantation step of the top-down fabrication process. Central to the strategy is the incorporation of on-chip ion-detector electrodes. During the implant process, a keV phosphorus ion produces electron-hole pairs via impact ionisation, which are detected in an external circuit. In-situ detectors fabricated at UNSW have shown efficiencies exceeding 97%.

A detailed fabrication process which integrates Al detector electrodes with nanoscale A and J-gates and SET read-out devices was also finalised during 2001. Following the commissioning of a new electron beam lithography system in 2001, we now routinely achieve sub-20nm feature sizes with an alignment accuracy of order 50nm.

Quantum Device Measurement
This year has seen the fabrication of a QC readout simulation device developed to test the principle of readout by detecting spin dependent single electron tunnelling processes. Here the P atoms in the solid-state quantum computer are simulated with two metal dots connected by a tunnel barrier, forming a double-dot system (Fig 5). Control gates used to push single electrons from one dot to the other, and the twin-SETs are then used to detect this single charge motion.

Figure 5 shows low temperature measurements of these second generation twin-SET devices, in which we have clearly demonstrated the controlled transfer of single electrons between the two dots in the simulation device. Single electron transfers are detected as a sharp change in both of the SET outputs simultaneously. However, signals due to unwanted charge noise tend not to affect both SETs simultaneously . By correlating the outputs of the two SETs we are thus able to clearly identify the single charge transfer events, and reject spurious signals that would interfere with QC readout.

Figure 4 Second Generation twin-SET QC readout simulation devices fabricated at UNSW. On the left is an optical micrograph of a chip containing 16 twin-SET devices; shown on the right is an SEM image of the active area of one of the devices.

Figure 5 Detection of single electron transfer between the two metal dots in a generation-II SSQC simulation device. Upper panel shows the outputs of the two SETs as electrons jump from one dot to the other under the influence of an applied electric applied electric field. The lower panel shows the correlated output of the two SETs, which rejects charge noise, leaving only sharp peaks at each of the electron transfer events.