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SINGLE ELECTRON TRANSISTORS (SETs) in some ways represent
the ultimate in electronic device miniaturisation, in that their
behaviour is determined by the number of electrons contained within the
transistor
which, in the case of some SETs, can be reduced to a single electron. SETs
are so sensitive to electron number that it is possible to count the electrons
one-by-one as they populate the device. Their ability to "count" electron states
makes them important as memory devices, while their high sensitivity to
local charge means that they can be used as ultra-sensitive electrometers. This
latter property is of significant interest for solid state implementations of
quantum computers.
The operation of SETs relies on a phenomenon known as
Coulomb blockade, which results from the discrete nature of electrical charge.
Like a conventional transistor, an SET has three basic electrodes a source,
a drain, and a control gate (see Fig. 1b). In addition, an SET has a small
island electrode, isolated from the source and drain by insulating barriers (Fig.
1c), through which electrons may transmit only via quantum
mechanical
tunnelling. If the size (and hence capacitance C) of this island is
very small, the charging energy (equal to
e2/C) required to add an extra electron
to the island can be greater than the available thermal energy
kBT. In this
case, conduction through the island is energetically forbidden and a
Coulomb blockade occurs. This blockade can be broken by varying the
electrostatic potential on the control gate,
effectively squeezing one electron at a time out
of the island.
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Researchers at the Semiconductor Nanofabrication Facility (SNF)
are studying both semiconductor SETs and metallic SETs, which
incorporate aluminium electrodes and
Al2O3 tunnel barriers, fabricated using a
sophisticated nanolithographic process
incorporating high-resolution electron-beam lithography and a shadow-mask
resist technology. Fig. 1(a) shows an example of an SET device fabricated at
SNF using this technique, in which the island electrode is deposited in an initial
Al evaporation, while the other electrodes are deposited in a second evaporation
in which the Al is directed at the surface from a different angle. Between
these two evaporations the Al is allowed to oxidise, in a tightly controlled process, forming the thin
Al2O3 tunnel barrier (see Fig. 1(c)).
The shadow-mask process, which has many detailed steps, relies on the
ability to create a thin but rigid layer of polymer resist which can
significantly overhang a lower layer of thick resist,
to produce a large covered cavity. Fig. 2 shows such a resist overhang
fabricated at SNF, in which a 1micron-wide layer of thin resist is supported by a
narrow pillar of resist just over 100nm wide. The top layer, which is only 50nm
thick, then overhangs the lower layer by about 400nm on either side. In Fig. 2, a
layer of Al has been deposited over the entire structure from above and the shadow
of the top layer is clearly evident. If the Al is evaporated at an angle away
from the vertical, it is possible for the metal to deposit underneath the overhang.
Using this process and a clever design of the window in the top layer, one can fabricate the SET devices shown in
Fig. 1.
Rolf Brenner, Tilo
Buehler, Robert Clark,
Andrew Dzurak & Nancy Lumpkin
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